Combinatorial cell design for CMOS libraries

Abstract

This paper presents a methodology for designing primitive gates in a CMOS standard cell library. The topological design space of the gates is restricted to varying the p- to n-fet width ratio and the optimal ratio is determined analytically. With topology thus fixed, gate size selection is performed as follows. A measurement error on a gate is defined to quantify the discrepancy resulting from replacing the size required by a synthesis sizing algorithm with a size available in a discrete cell library. The criterion for gate size selection is a set of gate sizes that minimizes the cumulative error of a prescribed measurement. Optimal solutions to the gate size selection problem targeting size and delay measurements are presented for cases where the probability distribution and the delay equations are simple. A realistic probability distribution is obtained using a sample space of gates derived from a group of designs that is synthesized under the semi-custom synthesis methodology. A “delay-match” (minimizing delay error) and a “size-match” (minimizing size error) set of gate sizes are obtained numerically, and are subsequently realized as discrete cell libraries. The previous group of designs are synthesized using the two selected cell libraries and two other cell libraries, one with “equal-spacing” of cell sizes and the other with “exponential-spacing” of cell sizes. The “size-match” library gives the best overall slack and area results.