Combination of radix-2<sup>m</sup> multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers

Abstract

This paper addresses the design of efficient 2's complement 64-bit array multipliers. We propose the combination of radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> dedicated multiplier blocks and adder compressors that leads to the reduction of partial product lines, and hence to the higher performance and least power consumption. The flexibility of the architecture allows for the easy construction of multipliers for different values of m. With the use of optimized radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> dedicated multiplication blocks the multiplication can be naturally extended up for radix-256 multiplication. Since in the radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> multiplier the number of partial lines is reduced, by the multiplication of m bits at a time, we have used a combination of 4:2, 8:2 and 16:2 adder compressors in order to speed-up the addition of the simultaneous operands. We present results of area, delay and power consumption by using SIS and SLS (Switch Level Simulator) tools. The results show that combining the use of dedicated multiplier modules with adder compressors the radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> array multipliers are more efficient in terms of delay and power consumption when compared with both a Radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> array multiplier with Ripple Carry Adders (RCA) in the partial product lines, previously presented in literature, and the Modified Booth multiplier.