Collaborative Packet Header Parsing in NetFPGA-Based High Speed Switches

Abstract

Packet parsing is an important task performed by network elements, that involves traversal of a complex parser graph. At very high link bandwidths, the parsing time has to be reduced significantly. This letter proposes a collaborative approach, where the ingress switch parses the header stack and passes an unique parser code (UPC) to downstream routers, that use this UPC to compute the header offsets without parsing. This approach was implemented on a Xilinx NetFPGA based programmable data plane switch, and was shown to reduce packet processing time by nearly 8%.