Collaborative error control method for sequential logic circuits

Abstract

A collaborative method is proposed to detect soft errors in combinational logic and memory elements of sequential logic circuits. The proposed match functions examine the current flip-flop values and the incoming flip-flop inputs produced by combinational logic to recognize the presence of soft errors. Conventional error control methods for sequential circuits focus on protecting the memory elements, rather than combinational logic. Unfortunately, the error rate of combinational logic is approaching that of memory elements as technology scales down. Modular redundancy approaches, such as triple modular redundancy (TMR), can simply protect both combinational logic and memory elements at the cost of large area and power. We apply the proposed collaborative method to a binary counter and one ITC'99 benchmark circuit to assess the system failure rate and error protection overhead. Gate-level simulation results show that our approach improves the system failure rate more than one order of magnitude over TMR. Synthesized netlists show that our method consumes 40% less area and 50% less power than TMR. Experimental results also show that our method achieves a comparable error detection rate to an error control coding method with 34% dynamic power reduction.