Abstract
The second and final version of ColdADC, called ColdADC_P2, is presented. ColdADC_P2 is a 16-channel, 12-bit, 2 MS/s digitizer application-specific integrated circuit (ASIC) intended for use inside the DUNE Far Detector. ColdADC_P2 contains two 16 MS/s pipelined analog-to-digital converters (ADCs) that each digitizes the output of eight sample-and-hold amplifiers (SHAs). Because the application requires immersion in liquid argon (LAr), ColdADC_P2 was developed using specialized design techniques for long-term reliability in cryogenic environments and a customized cryogenic standard cell library. ColdADC_P2, with a die area of approximately 52.4 mm<sup>2</sup> and fabricated in 65-nm CMOS technology, achieves 130-<inline-formula> <tex-math notation="LaTeX">$\mu \text{V}$ </tex-math></inline-formula> rms noise performance and 11.8-bit effective-number-of-bits (ENOB) at a temperature of 77 K, with channel-to-channel crosstalk of < 0.06% while dissipating 338 mW (21 mW per channel). Residual nonlinearity that is consistent with dielectric absorption in the capacitors internal to the ADC is corrected using a lookup table.
Highlights
The Deep Underground Neutrino Experiment (DUNE) is an international experiment for neutrino and proton decay studies [1]
The Far Detector will consist of four liquid argon (LAr) Time Projection Chambers (TPCs), each with a volume containing approximately 17 kTon LAr total mass
We have found that the correction polynomial calculated for one channel in a given chip can be used to correct the linearity for the corresponding channel in a different chip
Summary
The Deep Underground Neutrino Experiment (DUNE) is an international experiment for neutrino and proton decay studies [1]. ColdADC_P2 is designed to work together with two other ASICs: a preamplifier (LArASIC) [2] and a digital data aggregator (COLDATA) [3]. ColdADC_P2 is a 16-channel, 12-bit, 2 MS/s digitizer. The first prototype of the ASIC, called ColdADC_P1 [5], was fully evaluated and successfully operated in a LAr Time Projection Chamber (LArTPC). To facilitate prototype evaluation and testing, ColdADC_P2 was designed to be fully functional across a wide temperature range. The output of each SHA bank is digitized by a self-calibrated 12-bit, 16 MS/s Pipelined ADC. The Pipelined ADC in ColdADC_P2 uses a conservative design with digital selfcalibration as discussed below. The individual stages of the Pipelined ADC are scaled in area and bias current to minimize power dissipation.
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