Coherent Chip-Scale Modeling for Copper CMP Pattern Dependence

Abstract

AbstractIn this research, we present an improved and coherent chip-scale model framework for copper bulk polishing, copper over-polishing, and barrier layer polishing. The integration of contact wear and density-step-height models is more seamlessly implemented and addresses inherent shortcomings of the previous model. In the new model, a local density is used instead of the effective density computed by way of a planarization length, and only a contact wear coefficient is used to characterize the long-range planarization capability, thus avoiding the conflict between the planarization length and the contact wear coefficient in capturing topography variation. In addition, the pressure computed for each 240×240 μm block using contact wear is further redistributed, using a linear height vs. pressure model, among 40×40 μm cells within that block. The same model framework is used for different polishing steps, so that it is possible to directly compare basic process characteristics, such as pad stiffness, of different polishing stages. Results with the new model show a significant improvement of the modeling accuracy to less than 100 Å of root mean square error. Furthermore, the new model framework can be adapted for the modeling of multi-level metallization processes.