Co-design, modelling and simulation challenges: From components to systems

Abstract

Advanced packaging and heterogeneous integration are major drivers for future electronic systems. Examples include 3D-IC, wafer level packaging, embedded components, and system in package. To realize the benefits of advanced packaging and heterogeneous systems integration, design flows, circuit-level simulations, and physics-based modelling will need to address the challenges for chip-package-system co-design. At present design and modelling is disjointed across the chip-package-system domains where single point analysis tools are used within each domain. To address the requirements for future heterogeneous systems and design productivity there is a need for advances in co-design, modelling, and simulation. This paper will discuss these challenges and provide an overview of the co-design, modelling, and simulation activities taking place within the new IEEE Heterogeneous Integration Roadmap.