Code generator for parallel implementation of intensive algorithms on multiple DSP chips

Abstract

Many intensive and real-time signal processing applications for example in control, speech synthesis/recognition and image processing, have computational requirements which are too high for implementation on single DSP processors. Parallel implementation on multiple DSP processors provides an attractive solution to this problem. This paper presents a code generator which is capable of automatically producing parallel code for a multiprocessor hardware platform. The generator makes use of special code skeletons to abstract away from the hardware platform being used, and hence providing a high degree of flexibility in the choice of platforms. By using a consistent interface to these skeletons one can easily retarget the same signal processing application to different hardware systems. The design philosophy and architecture of the code generator as well as the types of multiprocessor hardware platforms used are presented and discussed. (10 pages)