Abstract
In this paper, we demonstrate the feasibility of building a memristor-based approximate accelerator to be used in cooperation with general-purpose $\times 86$ processors. First, an integrated full system simulator is developed for simultaneous simulation of any multicrossbar architecture as an accelerator for $\times 86$ processors, which is performed by coupling a cycle accurate Marss $\times 86$ processor simulator with the Ngspice mixed-level/mixed-signal circuit simulator. Then, a novel mixed-signal memristor-based architecture is presented for multiplying floating-point signed complex numbers. The presented multiplier is extended for accelerating convolutional neural networks and finally, it is tightly integrated with the pipeline of a generic $\times 86$ processor. To validate the accelerator, first it is utilized for multiplying different matrices that vary in size and distribution. Then, it is used as an accelerator for accelerating the tiny-dnn, an open-source C++ implementation of deep learning neural networks. The memristor-based accelerator provides more than $100\times $ speedup and energy saving for a $64\times 64$ matrix-matrix multiplication, with an accuracy of 90%. Using the accelerated tiny-dnn for the MNIST database classification more than $10\times $ speedup and energy saving along with 95.51% pattern recognition accuracy is achieved.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.