Cobalt CMP Development for 7nm Logic Device

Abstract

Cobalt metallization for CA (contacts) and TS (trench silicide) of 7nm logic device may dramatically reduce resistance and improve 5-7% performance compared to its counterpart tungsten. This new integration scheme requires novel cobalt deposition, CMP, cleaning and etching processes. This study presents the advancement of cobalt CMP development in GLOBALFOUNDRIES Inc.. Two-step CMP process was developed. Overburden cobalt was removed and polishing was stopped on the liner material via endpoint detection during the bulk CMP. Bulk CMP was followed by buff CMP, where the liner material and a certain amount of ILD films were removed. At first, the effect of polish pressure and sliding velocity on blanket cobalt removal rate was investigated. Results showed the prestonial relationship. Subsequently, process parameters (polish pressure, sliding velocity, over polish time, etc.) were optimized for the bulk CMP. End point was captured successfully and was stable at the optimized process conditions. In addition, process had wide over polish time window due to good stop ability of the bulk slurry on the liner material. During buff CMP, removal rate selectivity between cobalt, liner, and ILD films were studied and compared for different types of slurries with different components concentration. Higher liner removal rate and lower cobalt/ILD rate were achieved at an optimized slurry components concentration. Finally, cleaning solutions and process parameters were optimized. Surface topography (dishing, erosion, etc.) and defects post cobalt CMP were extensively characterized. Results demonstrated comparable CMP performance between cobalt and tungsten. Figure 1