Co-Optimization Between Static and Switching Characteristics of LDMOS With p-Type Trapezoidal Gate Embedded in Drift Region

Abstract

In this article, a novel p-type trapezoidal gate (PTG) lateral double-diffused MOSFET (LDMOS) is proposed and investigated by the 3-D TCAD simulation. The results reveal that the PTG LDMOS boasts a reduced gate-to-drain charge ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}_{\text {GD}}$ </tex-math></inline-formula> ) while maintaining an acceptable breakdown voltage (BV) and specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ \text{ON},\text {sp}}$ </tex-math></inline-formula> ). Compared with conventional LDMOS, a better tradeoff between the static figure of merit (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> , FOM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text {S}}\,\,=$ </tex-math></inline-formula> BV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ \text{ON},\text {sp}}$ </tex-math></inline-formula> ) and the dynamic figure of merit (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> , FOM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text {D}} = {R}_{ \text{ON},\text {sp}} \cdot {Q}_{\text {GD}}$ </tex-math></inline-formula> ) is realized. In the ON-state, the p-type polysilicon gate embedded in the drift region induces multiple plane majority-carrier accumulation layers, leading to a decrease in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ \text{ON},\text {sp}}$ </tex-math></inline-formula> . In the OFF-state, the metal–insulator–semiconductor (MIS) capacitor, which is composed of extended trench gate, gradual trapezoidal oxide, and N-drift. assists in depleting the drift region. Therefore, the doping concentration of drift region can be significantly lifted, and the BV is increased. Besides, the p-n junction capacitor composed of p-type and n-type polysilicon isolates the field coupling between gate and drain, and the gate-to-drain capacitor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {GD}}$ </tex-math></inline-formula> ) is thus reduced. Compared with multiple-plane electron accumulation layer LDMOS (MAL LDMOS) and split triple-gate LDMOS (STG-LDMOS), <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}_{\text {GD}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ </tex-math></inline-formula> of our proposed PTG LDMOS are shrunk by 34.3% and 54.4%, respectively. In general, the proposed PTG LDMOS achieves a better tradeoff between the static and switching characteristics.