Abstract

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

Highlights

  • Advances in techniques employed in wireless sensor systems have enabled the creation of novel biomedical applications [1,2]

  • Neural interface systems including micro-electrode arrays and signal processing circuits have been studied to identify human brain functions based on the weak electrical signals caused by the activity of nerve cells in the brain [3,4,5,6,7,8,9,10]

  • The signals obtained from the neural interface are essential for realizing brain-machine interfaces and supporting the lack of information in the brain caused by disorders and diseases

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Summary

Introduction

Advances in techniques employed in wireless sensor systems have enabled the creation of novel biomedical applications [1,2]. For realizing wireless communication and power transmission to the implanted neural interface on the brain surface, several technologies that integrate passive components (e.g., an antenna on a flexible film) with high-performance active circuits have been studied [18,19,20,21,22]. There is a need for a technique that can be used for mounting CMOS IC chips on a very thin film device.

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