Abstract
The High Luminosity LHC (HL-LHC) will provide unprecedented instantaneous and integrated luminosities. The CMS electromagnetic calorimeter (ECAL) will face a challenging environment at the HL-LHC: higher event pileup, higher radiation levels for the crystals and photo-detectors, and a higher rate of anomalous signals from the Avalanche Photodiodes (APDs) used for the light readout in the ECAL Barrel. A redesign of the ECAL electronics (including an increase in trigger rate and latency) is planned in order to mitigate these challenges and to maintain the excellent physics performance of the detector.
Highlights
The legacy front end electronics system, see figure 1, is based on the Multi Gain Pre-Amplifier (MGPA) [4], a 3 gain pre-amplifier ASIC and the AD41240 [5] a multi-channel 12 bit ADC, together yielding a 16 bit dynamic range with an LSB of 40 MeV
The token ring chip set was developed for the CMS silicon strip tracker and the off detector controller module was a joint development between the CMS electromagnetic calorimeter (ECAL) and the CMS silicon tracker
The CMS ECAL electronics system is performing to specification but, as the HL-LHC is planned to deliver significantly higher instantaneous luminosities, important modifications are required
Summary
The legacy front end electronics system, see figure 1, is based on the Multi Gain Pre-Amplifier (MGPA) [4], a 3 gain pre-amplifier ASIC and the AD41240 [5] a multi-channel 12 bit ADC, together yielding a 16 bit dynamic range with an LSB of 40 MeV. Data from the ADCs is input to a digital ASIC, the FENIX [6] implementing a digital pipeline, primary event buffer, and a trigger primitive generator. The trigger primitive generator calculates an energy sum based on 5×5 crystals in addition to two feature bits:. The spike flag bit is calculated by comparing each ADC value in a phi strip to a threshold, yielding five bits of information. The token ring architecture is somewhat vulnerable as, in principle, any node failure risk to prevent a whole ring from operating. This risk is mitigated by a node bypass feature. All ASICs were implemented in the well-established 250 nm radiation tolerant CMOS process with design features intended to make the ASIC more robust against single event upsets (SEU)
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