CMOS Technology Scaling for System-On-Chip Integration - Past, Present and Future

Abstract

The challenges of System-on-Chip (SoC) technology scaling are reviewed. It is shown that the key ingredients of an SoC process technology, including high performance logic transistors, low power transistors, high voltage transistors, memory, passives, analog and RF features are all benefited by Moore's Law. State-of-the-art CMOS technologies are powered by not just dimensional scaling, rather it incorporates the introduction of innovative device structures, development of the new materials and construction of new manufacturing equipment. It is expected that Moore's Law and CMOS scaling will continue in the near future, being powered by 3-D innovations in transistors, interconnects and packaging, supported by new materials and equipment.