CMOS NAND and NOR Schmitt circuits

Abstract

Original solutions of m-input NAND and NOR logic circuits with hysteresis in the transfer characteristics are proposed. Multiple inputs are done similarly to standard NAND and NOR logic circuits. The logic circuits proposed in this paper consist of 2 m + 1 paris of enhancement CMOS transistors. The hysteresis voltage depends on supply voltage and transistor geometry. The proposed solutions always guarantee hysteresis, even with very large process variations. The noise immunity is typically greater than 50% of supply voltage. Analysis using simple device models together with computer simulations and experimental results is given.