CMOS Low-Cost and Wide-Range Time-To-Digital Converter

Abstract

Low-cost and wide-range time-to-digital converter (TDC) using all-digital CMOS design is presented in this study. The conventional pulse-shrinking mechanism applied in an all-digital delay line (DL) adopts a short channel length ( $L$ ) of MOS transistor to achieve a high time resolution. However, the delay time of the DL was short to result in a narrow measurement range. To obtain a sufficient delay time for wide enough measurement range, the DL with extremely long stages is required to increase the circuit area unavoidably. For low-cost and wide-range demands, a longer $L$ of the transistor can be applied to effectively improve the area and measurement range both. However, the long $L$ decreases the time resolution. In this study, an all-digital pulse-mixing scheme (PMS) is used for significant resolution improvement. The proposed TDC was implemented in a TSMC 0.35- $\mu \mathrm{m}$ CMOS process for verification. Furthermore, the NAND-based DL is used to save the circuit area for the same range. The occupied area of the study is only 0.0103 mm2. Without considering the counter, it achieves a nearly 20% improvement in circuit area compared with INV-based one. The experimental results show that this all-digital TDC owns the benefits of small circuit area, high resolution, and wide measurement range.