CMOS logarithmic curvature-corrected voltage reference using a multiple differential structure

Abstract

A new superior-order curvature-corrected voltage reference will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing the linear and the superior-order curvature corrections. An original CTAT (complementary with absolute temperature) voltage generator will be proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the voltage reference, having two great advantages: an important reducing of the circuit silicon area and an improved accuracy. The superior-order curvature-correction will be implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PPAT (proportional with absolute temperature) and PTAT/sup 2/. In order to obtain a low-voltage operation of the circuit, the classical MOS transistor, which implements the zero-order compensated voltage reference, will be replaced by a DTMOS (dynamic threshold MOS) transistor. The SPICE simulations confirm the theoretical estimated results, showing a temperature coefficient under 9.4 ppm/K for an extended input range 173 K < T < 423K and for a supply voltage of 2.5V and a current consumption of about 1/spl mu/A.