CMOS High-Speed 1/14 Dynamic Frequency Divider

Abstract

A dynamic frequency divider is capable of operating at twice the frequency of a static divider. The clocked dynamic inverter type flip-flop divider is adopted for use as a dynamic frequency divider. The dynamic divider is based on the C2MOS (Clocked CMOS) master-slave concept. The flip-flops are clocked by a single clock input. The dynamic divider was designed to divide its input by 2n where n denotes the number of divider stages. This synchronous dynamic divider can divide a sine wave input at a maximum frequency of 2.7GHz. Our dynamic divider is implemented on the Silterra 0.1 8um CMOS technology, and it operates with a 1.8V power supply. To demonstrate the capability of the dynamic divider, this paper will compare the dynamic divider to a static 2 divider. The dynamic divider is faster and has about half the device complexity of a static divider.