CMOS Development and Optimization, Scaling Issue and Replacement with High-K Material for Future Microelectronics

Abstract

development and optimization of Silicon technology has been guided by CM OS scaling theory (1) and predications made by Semiconductor Industry (SIA) in the International Technology Roadmap for Semiconductor (ITRS). With the trend of scaling down of Complementary M etal Oxide Semiconductor (CMOS) transistor as Moore's Law (2) requires replacement of conventional silicon dioxide layer with the higher permittivity material for gate dielectric. As the silicon industry moves to 32nm technology node and beyond complaints like leakage and power dissipation dominates. M anaging such issues are crucial factors for reliable high speed operation and chip design. Although scaling will continue for couple of decades but device geometries reaches to atomic size and limitation of quantum mechanical physical boundaries. To address these problems there is need of innovation in material science & engineering, device structure, and new nano devices based on different principle of physics. Here we have elaborated about scaling issues and alternate high-k dielectric for M etal Oxide Semiconductor Field Effect Transistor (M OSFET). Introducing a high-k material may replace today's silicon dioxide technology and can also provide extendibility over several generations. C-V analyses have been studied for various M OS capacitor with conventional SiO2 and also with high-k material like Gd 2O 3, ZrO2, HfO2, and TiO2.