CMOS DESIGN OF TREE MULTIPLIER USING LOW POWER AND AREA EFFICIENT FULLADDER

Abstract

Digital electronic computations started with the introduction of vacuum tubes. But implementation of larger engines became economically and practically infeasible. The invention of the transistor, followed by the introduction of the bipolar transistor led to the first successful IC logic family, TTL (Transistor-Transistor Logic). Next was the turn of the MOS digital integrated circuit approach. As electrons have higher mobility than holes, NMOS was preferred later so processors used NMOS-only logic, with higher speed relative to the PMOS logic. But later, NMOS-only logic started suffering from the same problem: power consumption. Finally the balance tilted towards the CMOS technology. In case of CMOS, addition of a single input increases the device count by 2 and thus increases the propagation delay. New logic styles were developed to minimise the propagation delay and chip area. We present high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). Wallace high-speed multipliers use full adders and half adders in their reduction phase. Half adders do not reduce the number of partial product bits. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity. A modification to the Wallace reduction is presented that ensures that the delay is the same as for the conventional Wallace reduction. The modified reduction method greatly reduces the number of half adders; producing implementations with 80 percent fewer half adders than standard Wallace multipliers, with a very slight increase in the number of full adders.