CMOS design of the Hao-Vandewalle model of neural associative memory

Abstract

The design of the Hao–Vandewalle (1992) model of neural associative memories is presented. The model consists of three layers with neurons in the hidden layer and the output layer. There are weighted forward connections from the inputs to the hidden neurons and from the hidden neurons to the output neurons and there are no connections within the hidden layer or the output layer. This model utilizes nonlinear functions for the neurons in different layers and is different from the traditional three-layer Multilayer Perceptron (MLP). One important feature of this model is that it employs an extremely simple weight set-up rule and all the resulting weights can only assume two different values, −1 and +1, which facilitates VLSI implementation. A four-point multiplier was designed based on a very high frequency transconductor to function as a synapse. The designs of the hidden neuron and the output neuron for this model are also discussed. The implementation of a 5 × 4 CMOS Hao-Vandewalle Associative Memory is then presented.