CMOS Design of 10-bit Pipeline ADC having throughput 100 Mega-samples/second

Abstract

There is a tremendous demand for analog to digital converters in the continuously increasing digital world. They are the most significant mixed-signal blocks acting as the interface between the analog and the digital world. Integrating these analog circuits into digital systems is challenging as the digital circuits limit the speed and accuracy of the converters. A wide range of analog to digital converters is available. The pipeline analog to digital converters provide high throughput from few mega-samples per second to greater than 100 mega-samples/second and resolution ranging from eight to sixteen bits. This paper deals with behavioral and CMOS level modeling of 10-bit pipeline ADC. It has been observed that fully circuit level simulations take a lot of time. Hence, co-simulation is a better alternative. Here, co-simulation has been performed among the behavioral and circuit modules and their corresponding outputs have been compared. Finally, the throughput and INL/DNL has been calculated. Keywords—Pipeline ADC, throughput, mixed-signal, resolution, behavioral, CMOS.