CMOS current-mode integrating receivers for Gbytes/s parallel links

Abstract

This paper presents the design of fully differential current-mode integrating receivers for Gbytes/s parallel links. Both class A and class AB configurations are considered. The proposed receivers consist of a transimpedance front-end that provides a low and tunable matching impedance to the channels to accommodate current-mode signaling, an integrating stage that acts as a low-pass filter to suppress the transient disturbances coupled to the channels and receiver, and a regenerative sense amplifier to amplify the output voltage of the preceding integrator to full swing. The class AB configured sense amplifier provide a voltage gain that is twice that of class A sense amplifier, enabling a fast sensing and latching. The proposed receiver has been implemented in UMC 0.13 μ m , 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. Simulation results demonstrate that the proposed class current-mode integrating receivers provide full output voltage swing when the data rate is 2.5 Gbyte/s.