Abstract

Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 mu m n-well CMOS process achieved a -3 dB cutoff frequency (f/sub 0/) of 42 MHz; f/sub 0/ was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 mu A. Using a single 5 V power supply with a nominal reference current of 100 mu A, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm/sup 2//pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 mu m n-well CMOS process to verify the implementation of finite transmission zeros. >

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