Abstract
Anodization is a low cost, low temperature, technology compatible with post foundry integration, suitable for 3D high aspect ratio deposition. Anodic tantalum pentoxide is used at IMEC as dielectric for integrated high density 3D Metal-Insulator-Metal capacitors. To verify its compatibility with CMOS devices, a 0.13 µm technology has been electrically qualified before and after a post-processing/deprocessing phase including the anodization of a tantalum pentoxide layer at 40 V. Low evolutions, below 6 %, has been monitored on nFET/pFET threshold voltage and subthreshold current. Slight decrease and increase in the leakage current is observed on nFET and pFET devices, respectively. However the monitored values were still in tolerance range. Contact and interconnection integrity have also been verified by measuring contact and sheet resistance of each layer. The study show that all devices were still functional with no or very limited impact of anodization on the performance.
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