Abstract
Memory bandwidth and on-chip memory requirements are critical issues in motion estimation (ME) implementations for video compression. The H.264/AVC scalable extension (SVC) provides variable frame rate and resolution video in a compressed digital sequence with interlayer prediction, which complicates the problems of limited memory bandwidth and on-chip memory size. In this paper, an ME algorithm is proposed for the hardware encoder design of SVC that meets memory bandwidth and on-chip memory requirements. Clustered motion estimation and coding sequence reordering at macroblock and frame level processing are proposed. Compared with existing algorithms, the proposed algorithm has a 49.20% lower external memory bandwidth and reduces the on-chip memory requirement by 80.45% with video quality enhancements of up to 0.087, 0.090, 0.078, and 0.070dB for four-layer (FullHD-HD-D1-CIF) spatial scalability, respectively.
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