Abstract
This paper reports a partitioned gate tunneling current model for NMOS devices with an ultra-thin-1 nm gate oxide biased in triode and saturation regions. As verified by the experimentally measured data, this partitioned gate tunneling current model based on the three-segment approach, provides an accurate prediction of the gate current for the device with a long or short channel, biased in triode and saturation regions. For a long channel device, the gate tunneling current in the pre-saturation region of the channel dominates. For the short-channel case biased in the saturation, at a large drain voltage, the gate current may become negative due to the negative voltage drop in the gate oxide near the drain.
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