Clocked semi-floating-gate ultra low-voltage current mirror

Abstract

In this paper we present a low voltage current mirror based on clocked semi-floating-gate transistors used in low-voltage digital CMOS circuits. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. The proposed current mirror can operate at supply voltages below 200 mV. Two different current mirrors are described; the common gate- and the split gate current mirror. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90 nm CMOS process.