Clocked semi-floating-gate pseudo differential pair for low-voltage analog design

Abstract

In this paper we present an ultra low-voltage pseudo differential pair based on a clocked semi floating-gate transistor. The clocked semi floating-gate transistors are exploited to increase the current level for ultra low supply voltages and may be used in ultra low voltage mixed signal design. The pseudo differential pair may operate at supply voltages down to 250 mV. Simulated data for 90 nm CMOS process with a transistor threshold voltage equal to 250 mV is included.