Clock Period Minimization of Non-Zero Clock Skew Circuits

Abstract

It is known that the clock skew can be exploited as a manageable resource to improve the circuit performance. However, due to the limitation of race condition, the optimal clock skew scheduling does not achieve the lower bound of the clock period. In this paper, we propose a polynomial time complexity algorithm, which incorporates optimal clock skew scheduling and delay insertion, for the synthesis of non-zero clock skew circuits. The main advantages of our algorithm include two parts. First, it guarantees to achieve the lower bound of the clock period. Secondly, it also tries to minimize the required inserted delays under the lower bound of the clock period. Experimental data shows that, even though we only use the buffers in a standard cell library to implement the delay insertion, our approach still works well.