Abstract
Circuit Synthesis plays a very important role among all the digital integrated circuit backend design flow. For the purpose of reducing the clocks latence in the design flow, based on the traditional clock network synthesis method, this paper demonstrates a clock synthesis method, which based on clock mesh technology using IC Complier tool.
Full Text 
Sign-in/Register to access full text options
Sign-in/Register to access full text options 
Paper version not known
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
