Clock mesh synthesis through dynamic programming with physical parameters consideration

Abstract

In response to the evolving technological landscape, the traditional clock network architecture faces challenges in meeting the complexities of modern System-on-Chip (SoC) designs. While the clock mesh topology offers resilience against On-Chip Variation (OCV) fluctuations, its manual implementation leaves room for advancements in methodology and swift analytical techniques. This paper introduces an innovative clock mesh synthesis approach, leveraging dynamic programming algorithms and emphasizing compliance with critical physical implementation parameters. Our experimental results demonstrate a significant 26.6% reduction in power consumption compared to baseline methodologies. Moreover, it achieves an impressive average runtime reduction of 78.0% when contrasted with traditional simulation methods. These findings underscore the potential of our methodology to enhance the efficiency and power management of clock mesh designs.