Clock-less 8-bit SAR-ADC with delay-line based digital control circuit

Abstract

Aim of the present paper is to propose an 8 bit SAR-ADC architecture where no external clock signals or on-chip clock generation circuits are used. The digital control circuitry is designed around a delay line constituted by a cascade of monostables. The circuit was implemented in a bulk 350 nm CMOS technology. The core of the integrated circuit is about 1500 μm × 1500 μm. Post layout simulations for both static (DNL, INL) and dynamic (ENOB, SINAD, THD) Figure-of-Merits are reported. The obtained performance are well aligned with others claimed in the literature for clocked SAR-ADC architectures.