Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application

Abstract

As autonomous driving becomes commercialized, the requirements for safe and advanced integrated circuits for automotive applications have become stricter than at any other time. IS026262 (Road Vehicle Functional Safety Standard) determines the risk level associated with systematic and random failures and defines the level of risk reduction required to achieve safety levels for target applications by the automotive safety integrity level (ASIL). IS026262 has a metric for a system's ability to detect failures, diagnostic coverage (DC) and the requirement for ASIL is 90 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">%</sup> ,97 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">%</sup> , and 99% for grade B, C and D, respectively, for the single point fault metric (SPFM). Whereas several papers have been published to satisfy the high ASIL grade at SoC level, only a few works were reported at the IP level [1]–[3]. A paper was published for clock IP with various built-in self-tests [4], but none of the works have mentioned certification with ASIL grade. If the IP level satisfies the ASIL grade, additional verification is not required for ASIL certification at the SOC level. In this paper, efficient phase-locked loop (PLL) and oscillator (OSC) architecture and safety mechanisms to fulfill ASIL-D requirements are proposed.