Clock Gated 16-Bits ALU Design & Implementation on FPGA

Abstract

In the digital sequential circuit design a single input clock signal is common for all the sequential circuits and is mainly used for synchronization. As the clock signal does not carry any useful information it is the main cause of dynamic power dissipation at high frequencies. Thus the technique of clock gating is utilized for disabling the modules which are not active for a given time of operation. This paper describes the review, implementation and comparison of various VHDL based clock gating techniques and calculation of dynamic power dissipation for 16-bits ALU operation using 13 instructions. The functionality of the design has been simulated and tested using Xilinx ISE 14.7 simulation, synthesized using plan ahead and is implemented on Artix Tm_ 7(family), with device xC7A100T™ having package 3CSG324, NEXYS 4 DDR with 40nm FPGA board. Xilinx X-Power analyzer is used to carry out the power calculation at different operating frequencies of 100 MHz to 500 MHz.