Abstract
The LHCb experiment is upgrading part of its detector and the entire readout system towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity and increase its trigger efficiency. In this paper, the new timing, trigger and control distribution system for such an upgrade is reviewed with particular attention given to the distribution of the clock and timing information across the entire readout system, up to the FE and the on-detector electronics. Current ideas are here presented in terms of reliability, jitter, complexity and implementation.
Highlights
In order to remove the main design limitations of the current LHCb detector as described in the previous section, the strategy for the upgrade of the LHCb experiment essentially consists of removing the first-level hardware trigger (L0 trigger) entirely, to run the detector fully trigger-less
Each S-ODIN is associated with a sub-detector partition which effectively is a cluster of Readout Boards (TELL40) and Interface Boards (SOL40)
This is a major novelty with respect to the current LHCb experiment where fast control and slow control are sent over different networks
Summary
In order to remove the main design limitations of the current LHCb detector as described in the previous section, the strategy for the upgrade of the LHCb experiment essentially consists of removing the first-level hardware trigger (L0 trigger) entirely, to run the detector fully trigger-less. In order to remove the main design limitations of the current LHCb detector as described, the strategy for the upgrade of the LHCb experiment essentially consists of removing the first-level hardware trigger (L0 trigger) entirely, to run the detector fully trigger-less. All events will be available at the processing farm where a fully flexible software trigger will perform selection on events, with an overall output of about 20 kHz of events to disk. This will allow maximizing signal efficiencies at high event rates. The upgraded TFC system will be interfaced to all elements in the readout architecture by heavily profiting from the bidirectional capability of optical links and FPGA transceivers and a high level of interconnectivity. The TFC system will be responsible to transmit slow control (ECS or Experiment Control System) information to the FE, by means of FPGA-based electronics cards interfaced to the global LHCb ECS
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