Classification of Chip-Level Defect Types in Wafer Bin Maps Using Only Wafer-Level Labels

Abstract

Abstract Defective chips in wafer bin maps (WBMs) form different spatial patterns depending on the root causes of process failures. Therefore, the identification of defect patterns in WBMs can help practitioners identify the root causes. Previous studies have focused on wafer-level classification even though chip-level classification can provide additional information regarding defect locations and defect sizes. Chip-level classification is more challenging than wafer-level classification because existing chip-level classification methods require chip-level labels, which are laborious to collect. We propose a method for chip-level defect classification using only wafer-level labels based on weakly supervised semantic segmentation. We first train a classification network using wafer-level labels and extract class activation maps (CAMs), which are visualizations of the discriminative regions. We then generate chip-level pseudo-labels using the extracted CAMs and use these labels to train a segmentation network, which predicts chip-level defect types. Experimental results verify the effectiveness of the proposed method.