Class AB amplifier with noise reduction, speed boost, gain enhancement, and ultra low power

Abstract

This paper presents an approach that improves the cost-performance of an amplifier whose output noise (Vonoise) is lowered by narrow-banding filtering it, while slew rate (SR) and settling time (ts) are enhanced, when an imbalance is detected at the amplifier's input (V IN ) via a rail-to-rail (RR) minimum-current-selector (MCS). The contributions of the proposed circuit are (1) increasing the amplifier's gain without impeding its dynamic response by implementing a boot-strapped gain stage in a folded cascode transconductance amplifier, or FCTA (2) lowering V ONOISE and enhancing the amplifier's dynamic response, with a smaller size suppression capacitor, or C S , which lowers die cost and reduces the boost current consumption, or IDD (3) enhancing the amplifier's SR and ts, lowering the dynamic I DD , and improving the amplifier's power supply rejection, during the boost cycles, by utilizing a complementary MCS and a floating current summation, or FCS, circuits. Worst case simulations (WC), and Monte Carlo simulations (MC) simulations demonstrate the following: gain (Av) ∼ 120dB, ts ∼ 7μs to +/− 10mV with a rail-to-rail (RR) 1.5V step at V IN , V ONOISE at 1kHz ∼ 9μV/√Hz, unity gain band-width (fu) ∼5kHz, phase margin (PM) ∼ 80 degrees, current consumption (I DD ) ∼180nA, minimum operating V DD ∼1.2V, power supply rejection ratio (PSRR) ∼ 94dB, common mode rejection ratio (CMRR) ∼ 125dB. Approximate amplifier area is ∼70 μm/side in 0.18μm digital CMOS.