CIS Band Noise Prediction Methodology Using Co-Simulation of Camera Module

Abstract

This paper describes a CMOS image sensor (CIS) horizontal band noise reduction methodology considering on-chip and offchip camera module PCB design parameters. The horizontal band noise is a crucial issue for high quality camera of modern smartphone applications. This paper discusses CIS horizontal band noise mechanism and proposes the solution by optimization of design factors in CIS and camera module. Analog ground impedance value and bias voltage condition of pixel array transfer gate have been found to be effective optimization parameters. Through the real experimental data, we proved that proposed solution is instrumental in reducing the horizontal band noise.