Abstract
A new technique for designing self-testing VLSI circuits, referred to as Circular Self-Test Path, is presented. The Circular Self-Test Path is a feedback shift register (output of the last flip-flop is supplied to the first flip-flop) with a data compaction capability. A distinguishing attribute of self-testing chips designed using this technique is a low silicon area overhead, slightly exceeding that of scan path designs. A theoretical analysis and comprehensive simulation experiments are performed to demonstrate that the effectiveness of test pattern generation for the circular self-test path is comparable to that of an ideal pseudorandom test generator.
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