Circuit-level Design and Evaluation of STT-MRAM based Binary Winner-Takes-All Network for Image Recognition

Abstract

Recently it has been demonstrated that binary neural network (BNNs) can achieve satisfying accuracy on various databases with the significant reduction of computation and memory resources [1], which provides a promising way for on-chip implementation of deep neural networks (DNNs). To storage synaptic weights, the SRAM is traditionally utilized in the CMOS based ASIC designs for hardware acceleration implementation of DNNs. However, it has been proved to be extremely area- and power-inefficiency due to its large cell area $( >200 \mathrm {F}^{2})$and volatility, respectively. To overcome these issues, the emerging non-volatile spin transfer torque magnetoresistive RAM (STT-MRAM) with small cell area $(< 10 \mathrm {F}^{2})$recently has been proposed to implement synaptic weights instead of SRAM [2]. Moreover, STT-MRAM has been demonstrated at Gb chip-level by industry [3]. In this paper, a single-layer binary perceptron (BP) is proposed for image recognition, which can be implemented via the pseudo-crossbar array of 1T-1MTJ (STT-MRAM cell) as shown in Fig. 1(a). With the learning rule in [1], such BP was trained in an off-line manner on a set of $\mathrm {N}=30$patterns, including three stylized letters (‘z’, ‘v’, ‘n’) as shown in Fig. 1(b) [4], which also was used for testing. To classify these three stylized letters, we design a winnertakes-all (WTA) circuit as shown in Fig. 1(c), which is used as the peripheral inference circuit of proposed BP. Based on a physics-based STT-MTJ compact model and a commercial CMOS 40 nm design kit, the functionality of the proposed BP and WTA circuit have been demonstrated as shown in Fig. 2(a). Additionally, we also investigate the impact of TMR and device variations on the recognition rate as shown in Fig. 2(b)and Fig. 2(c), respectively. In summary, a STT-MRAM based binary synaptic array with a WTA circuit has been proposed for image recognition, which provides a promising solution for hardware implementation of BNNs on-chip.