Circuit Timing Signature (CTS) for Detection of Counterfeit Integrated Circuits

Abstract

Counterfeit integrated circuits (ICs) have been on the rise over the past decade and represent a major concern. Counterfeits impact the security and reliability of electronic systems particularly those deployed in critical applications. While there are several different types of counterfeit ICs in the supply chain (cloned, recycled, remarked, overproduced, etc.), reports indicate that recycled ICs constitute the majority of all counterfeit ICs in the market today. Such ICs are recovered from the scrapped boards of used devices. Since these ICs are identical to their unused counterparts in appearance, functionality, and packaging, detecting them can be challenging. It has been observed that path delays in recycled ICs will be larger than those in unused ICs due to the effects of silicon aging, such as negative/positive bias temperature instability (NBTI/PBTI) and hot carrier injection (HCI). In this chapter, a circuit timing signature (CTS) technique is presented to distinguish recycled ICs from unused ones. Specifically, a clock sweeping technique is employed both to measure the amount of path delay and to generate a timing signature for chips under testing. Due to the degradation in the field, the path delay distribution of recycled ICs becomes different from that of new/unused ICs, resulting in a different CTS. An authentication flow for accurately identifying recycled ICs is presented. Results show that statistical analysis can effectively separate the impact of process variations from aging effects on path delay. In addition, the CTS is extended to the detection of cloned ICs, overproduced ICs, and remarked ICs. A unique binary ID is generated based on the CTS of each IC. By checking the intrinsic IDs, cloned, overproduced, and remarked ICs can be effectively identified.