Circuit Partitioning for VLSI Layout

Abstract

Partitioning is a technique to divide a circuit or system into a collection of smaller parts (components). Circuit partitioning problem is a well-known NP hard problem and requires efficient heuristic algorithms to solve it. The problem involves dividing the circuit net list into two subsets. The balanced constraint is an important constraint that obtains an area-balanced layout without compromising the min-cut objective. The number of edges belonging to two different partitions is the cut-cost of a partition. This chapter deals with multi-objective genetic algorithms for the optimization of two objectives: area imbalance and cut cost. The objective is to separate the cells into two partitions so that the number of interconnections between the partitions can be minimized and the cells are evenly distributed across the layout surface. MCNC benchmark circuits are used to validate the performance of the multi-objective evolutionary algorithms.