Abstract
Because the selfheating effect (SE) influences the performance and reliability of gate oxide and interconnect lines, and SE is affected by circuit operation such as operating frequency, the spatial distribution and dynamic behaviors of SE are important in a robust circuit design. In this work, we propose new thermal equivalent circuit model of ITRS roadmap based 5 nm bulk-FinFETs, which is based on analysis of the Boltzmann phonon transport and commercial 3D-technology computer-aided design simulation. By implementing the proposed model into a SPICE circuit simulator, circuit designers can co-optimize the electro-thermal behaviors of nanoscale bulk-FinFETs at the circuit level.
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