Circuit-level reliability requirements for Cu metallization

Abstract

Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrate significant differences because of differences in interconnect architectural schemes. The low critical stress for void nucleation at the Cu and interlevel diffusion-barrier interface leads to varying failure characteristics depending on the via position and configuration in a line. Unlike Al technology, a (jL) product-filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. A methodology and tool for circuit-level interconnect-reliability analyses has been developed. Using data from the literature, the layout-specific circuit-level reliability for Al and dual-damascene Cu metallizations have been compared for various circuits and circuit elements. Significantly improved test-level reliability in Cu is required to achieve equivalent circuit-level reliability. Moreover, the required improvement will increase as low-k/low-modulus dielectrics are introduced, and as liner thicknesses are reduced.