Circuit-Level Layout-Aware Modeling of Single-Event Effects in 65-nm CMOS ICs

Abstract

We present a convenient layout-aware circuit-level modeling technique based on two modeling approaches: single spot and distributed circuit representing the diffusion- and circuit-driven charge collection processes correspondingly. The calibration is based on a joint comprehensive analysis of experimental data for 6T SRAM cells: cross-section dependences, error maps, and single-event upset multiplicity. This paper presents the results of both calibration and simulation for the devices manufactured by the TSMC 65-nm technology.