Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM

Abstract

Single-transistor floating-body RAM (FB-RAM) cells present a promising alternative for scalable high-density storage since both access and storage elements are implemented using a single FET-based device. Unlike embedded dynamic RAM (eDRAM) technology, the concept is fully scalable with decreasing technology nodes. However, to make the concept truly usable, special biasing conditions of the device need to be considered; hence, the peripheral elements must be designed accordingly. We propose an approach of FinFET-based cell and peripheral circuit to provide compatible bias conditions for efficient write-read and hold conditions. The periphery is based on the synchronized bit line and word line driver schemes capable of providing compatible voltages to the selected and unselected lines during the different operations. The full circuit has been validated, and the concept has been demonstrated by simulations using the silicon-proven model cards and design decks.