Abstract
With the ever-increasing complexity, circuit verification at the full-chip level is a major bottleneck in the design of VLSI circuits. This paper presents procedures that verify a given CMOS/BiCMOS VLSI circuit for its compliance to a set of pre-defined rules or design styles. Predefined rules range from simple connectivity and sizing rules to specific circuit topologies ensuring acceptable circuit speed, reliability, and signal integrity. Our compliance checks operate on transistor-level circuit netlists, which may contain back-annotated parasitics. The procedures and rules have been implemented in a checker called Elecdra. VLSI circuits with over 3 million devices have been successfully verified by Elecdra at the full-chip level.
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