Abstract
Low-voltage and low-power digital design has to be performed at several levels such as architecture, logic and basic cell levels, while considering activity, capacitance, frequency and supply voltage reduction. Comparison of energy-efficient architectures will be performed while using energy/operation and throughput. Examples of activity and capacitance reduction will be provided for a low-power digital cell library as well for logic modules. However, supply voltage reduction is a more effective way to save power. Operating frequency as well as supply voltage reduction in parallelized logic circuits results in a reduction of the power consumption of several factors while maintaining the same throughput.
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