CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems

Abstract

Recently, annealing processors based on the Ising model have received rising attention as efficient alternative hardware for solving combinatorial optimization problems. After mapping a problem to the hardware Ising model, we can observe the natural convergence behavior of the Ising model and find potential solutions to the problem. The quantum annealing processor has shown effectiveness in finding better solutions to the problems by using quantum bits (qubits) with annealing based on their quantum tunneling behaviors. However, the annealing processor based on the emerging quantum technology faces challenges such as limited scalability, high energy consumption, and operating costs due to the extremely low operating temperature. As a low-cost alternative, a CMOS annealing processor has been recently developed and drawn increasing attention thanks to the advantages over its quantum counterpart, including better scalability and lower energy consumption. In this work, we present a digital CMOS annealing processor with in-memory spin operators and register spins. The proposed CMOS annealing processor achieves > <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula> energy efficiency and faster operation than state-of-the-art works.